To save power, the core circuitry of a device, e.g., a microprocessor, operates on a predetermined voltage level, even though the device must communicate externally using an input/output (I/O) voltage level which is higher than the predetermined voltage used by the core of the device. For example, a microprocessor operates on logic levels of high (H) and low (L) having voltage levels of 2 volts (V) and 0 V, respectively, although the device is connected to a 3.3 V power rail for use in external communications. When the core of the device outputs a signal, the device uses an I/O buffer to convert the voltage levels of 0 V and 2 V to output voltage levels of 0 V and 3.3 V.
FIG. 1 is an illustration of an inverter 2 which may be used for such a voltage conversion. A source terminal of a PMOS transistor P.sub.I1 is connected to a predetermined source voltage V.sub.CCIO of 3.3 V while a source terminal of an NMOS transistor N.sub.I1 is connected to a predetermined voltage V.sub.SSIO of 0V (ground voltage). The drain terminals of transistors P.sub.I1 and N.sub.I1 are connected to each other. The commonly connected gates of transistors P.sub.I1 and N.sub.I1 receive an input signal at an input terminal IN. When an input signal of 0 V from the internal device is applied at terminal IN, transistor N.sub.I1 is turned OFF, and transistor P.sub.I1 is turned ON such that inverter 2 outputs a signal of 3.3 V at an output terminal OUT. The inverter 2 outputs a signal of 0 V at output terminal OUT in response to an input signal of 2 V at input terminal IN.
In the latter case, however, both transistors N.sub.I1 and P.sub.I1 will be ON since there is a gate-source voltage V.sub.gs of 1.3 V, i.e., V.sub.CCIO -V.sub.IN. With both transistors P.sub.I1 and N.sub.I1 ON, there is a static current drain through inverter 2, undesirably consuming power as a result of static current drain.
FIG. 2 is an illustration of an inverting level shifter 4 used for voltage conversion, improved by avoiding static current flow induced power consumption. This circuit configuration is very similar to that of cross-coupled inverters with a static dc path cut off by transistor N.sub.L1 when a high input signal is applied at input terminal IN.
The source terminals of PMOS transistors P.sub.L3 and P.sub.L4 are connected to the source of voltage V.sub.CCIO. The drain terminals of PMOS and NMOS transistors P.sub.L3 and N.sub.L1 are connected to each other, and the drain electrodes of PMOS and NMOS transistors P.sub.L4 and N.sub.L3 are connected together. The gate of transistor P.sub.L3 is connected to output terminal OUT while a gate of transistor P.sub.L4 is connected to a drain terminal of transistor P.sub.L3. The gate of transistor N.sub.L1 is connected to a reference voltage V.sub.refn, e.g., 2.0 V. The gate of transistor N.sub.L3 and the source terminal of transistor N.sub.L1 are connected to input terminal IN. The source terminal of transistor N.sub.L3 is connected to the source of predetermined ground voltage V.sub.SSIO.
When an input signal of 0 V from the internal device is applied at terminal IN, transistors P.sub.L3 and N.sub.L3 are turned OFF while transistors P.sub.L4 and N.sub.L1 are turned ON, and level shifter 4 hence outputs a voltage level of 3.3 V at terminal OUT. When an input signal of 2 V is applied at input terminal IN, transistors P.sub.L3 and N.sub.L3 are turned ON while transistors P.sub.L4 and N.sub.L1 are turned OFF, and level shifter 4 outputs a voltage level of 0 V at terminal OUT.
After the voltage conversion, the voltage level of 0 V or 3.3 V from inverting level shifter 4 is applied to an output driver circuit of the I/O buffer. FIG. 3 is a schematic diagram of a conventional output driver circuit 6 connected to a capacitative load C.sub.load, representative of an external device connected to an output node N.sub.out.
The source terminal of a PMOS transistor P.sub.D1 is connected to the source of voltage V.sub.CCIO, e.g, 3.3 V, while a source electrode of an NMOS transistor N.sub.D1 is connected to the source of predetermined voltage V.sub.SSIO, e.g., 0 V. The drain of transistor P.sub.D1 is connected to the source of a PMOS transistor P.sub.D2, and a drain of transistor N.sub.D1 is connected to a source of an NMOS transistor N.sub.D2. The drains of transistors P.sub.D2 and N.sub.D2 are connected to an output node N.sub.out. The gate of transistor P.sub.D2 is connected to the source of voltage V.sub.SSIO while a gate of the transistor is connected to reference voltage source V.sub.refn, e.g., 2.0 V or 3.3 V. The gates of transistors P.sub.D1 and N.sub.D1 receive the converted voltage levels of 0 V and 3.3 V, respectively. The transistors P.sub.D2 and N.sub.D2 of FIG. 3 are optional. They are most often used to limit charge leakage through the device, or to lessen hot-electron caused device lifetime or performance degradation.
When an input signal of 0 V is applied to the gates of transistors P.sub.D1 and N.sub.D1, transistor N.sub.D1 turns OFF while transistor P.sub.D1 turns ON. Both transistors P.sub.D2 and N.sub.D2 are initially ON, but transistor N.sub.D2 turns OFF as the voltage level at node N.sub.out rises to 3.3 V. When an input signal of 3.3 V is applied to the gates of transistors P.sub.D1 and N.sub.D1, transistor N.sub.D1 turns ON while transistor P.sub.D1 turns OFF. The transistor N.sub.D2 is ON, and node N.sub.out drops to 0 V, which forces transistor P.sub.D2 to turn OFF.
As shown in FIGS. 1-3, inverter 2, level shifter 4 and output driver 6 are fabricated using CMOS technology. Due to advances, such devices are becoming smaller, the thickness of the transistor gate oxides is becoming thinner. For most semiconductor processes, when the thickness of the gate oxide becomes less than or equal to approximately 60 angstroms (.ANG.), a voltage greater than approximately 2.4 V-2.5 V across the gate oxide causes the oxide to break down. For example, if an input signal of 2.0 V is applied to the gate of transistor N.sub.L3, level shifter 4 of FIG. 2 outputs a voltage of 0 V at the output terminal OUT, and a voltage difference of 3.3 V exists between the bulk and gate of transistor P.sub.L3. If the gate oxide thickness is .ltoreq.60 .ANG., the gate oxide will break down, causing level shifter 4 to fail. Likewise, inverter 2 and output driver 6 will fail if the gate oxide thickness of the transistors is less than about 60 .ANG. for most processes.